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 SSG4435
-8A, -30V,RDS(ON) 20m[ Elektronische Bauelemente
P-Channel Enhancement Mode Power Mos.FET
RoHS Compliant Product
SOP-8
Description
The SSG4435 provide the designer with the best Combination of fast switching, ruggedized device design, Ultra low on-resistance and cost-effectiveness.
The SOP-8 is universally preferred for all commercial industrial surface mount application and suited for low voltage applications such as DC/DC converters.
0.35 0.49 1.27Typ. 4.80 5.00 0.100.25 3.80 4.00 6.20 5.80 0.25 0.40 0.90 0.19 0.25
45
o
0.375 REF
Features
* Low on-resistance * Simple drive requirement
D 8 D 7 D 6 D 5
0 o 8
o
1.35 1.75
Dimensions in millimeters
D
* Fast switching Characteristic
Date Code
4435SC
G
1 S 2 S 3 S 4 G
S
Absolute Maximum Ratings
Parameter
Drain-Source Voltage Gate-Source Voltage www..com Continuous Drain Current Continuous Drain Current Pulsed Drain Current
1
Symbol
VDS VGS ID@TA=25 C ID@TA=70 C IDM PD@TA=25 C
o o o
Ratings
-30
20 -8 -6 -50 2.5 0.02
Unit
V V A A A W
W/ C
o o
Total Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range
Tj, Tstg
-55~+150
C
Thermal Data
Parameter
Thermal Resistance Junction-ambient (Max)
Symbol
Rthj-a
Ratings
50
o
Unit
C /W
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 1 of 5
SSG4435
Elektronische Bauelemente -8A, -30V,RDS(ON) 20m[ P-Channel Enhancement Mode Power Mos.FET
Electrical Characteristics( Tj=25 C Unless otherwise specified)
Parameter
Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Gate Threshold Voltage Gate-Source Leakage Current Drain-Source Leakage Current (Tj=25 oC) Drain-Source Leakage Current (Tj=70 oC) Static Drain-Source On-Resistance
2 2
o
Symbol
BVDSS BVDS/ Tj VGS(th) IGSS IDSS
Min.
-30
_
Typ.
_
Max.
_ _
Unit
V V/ C V nA uA uA m[
o
Test Condition
VGS=0V, ID=-250uA Reference to 25 C,ID=-1mA VDS=VGS, ID=-250uA VGS= 20V VDS=-30V,VGS=0 VDS=-24V,VGS=0 VGS=-10V, ID=-8A VGS=-4.5V, ID=-5A
o
-0.037
_ _ _ _
-1.0
_ _ _ _
-3.0
100
-1 -5 20 35
_
_ _
_ _ 47 9.5 8
_
_ _ _
RDS(ON) Qg Qgs Qgd Td(ON) Tr Td(Off) Tf Ciss Coss Crss Gfs
_ _ _ _ _ _ _ _ _ _ _
Total Gate Charge
Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time 2 Rise Time Turn-off Delay Time Fall Time www..com Input Capacitance Output Capacitance Reverse Transfer Capacitance Forward Transconductance
nC
ID=-4.6A VDS=-15V VGS=-10V
30 20 120 80 2800 1400 350
_ pF nS
VDD=-15V ID=-1A VGS=-10V RG=6 [ RD=15 [
_
_ _
VGS=0V VDS=-15V f=1.0MHz
_
20
S
VDS=-10V, ID=-8A
Source-Drain Diode
Parameter
Forward On Voltage
2
Symbol
VDS
Is ISM
Min.
_
Typ.
-0.75
_ _
Max.
-1.2
Unit
V
Test Condition
IS=-2.1A, VGS=0V.
VD=VG=0V, VS=-1.2V
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)
_ _
-2.1 -50
A A
Notes: 1.Pulse width limited by safe operating area. 2.Pulse widthO 300us, dutycycleO2%.
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 2 of 5
SSG4435
Elektronische Bauelemente -8A, -30V,RDS(ON) 20m[ P-Channel Enhancement Mode Power Mos.FET
Characteristics Curve
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
www..com
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance v.s. Junction Temperature
http://www.SeCoSGmbH.com/
Fig 5. Maximum Drain Current v.s. Case Temperature
Fig 6. Type Power Dissipation
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 3 of 5
SSG4435
Elektronische Bauelemente -8A, -30V,RDS(ON) 20m [ P-Channel Enhancement Mode Power Mos.FET
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
www..com
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
Fig 11. Forward Characteristics of Reverse Diode
http://www.SeCoSGmbH.com/
Fig 12. Gate Threshold Voltage v.s. Junction Temperature
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 4 of 5
SSG4435
Elektronische Bauelemente -8A, -30V,RDS(ON) 20m [ P-Channel Enhancement Mode Power Mos.FET
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
www..com
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 5 of 5


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